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Instruction set architecture
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#	Item
671	Illusionist: Transforming Lightweight Cores into Aggressive Cores on Demand Amin Ansari University of Illinois [removed] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-01-25 16:46:06 Central processing unit Microprocessors Instruction set architectures Parallel computing DEC Alpha CPU cache Branch predictor Multithreading ARM architecture Computer architecture Computer hardware Computing
672	Technology in Higher Education Add to Reading List Source URL: www.cdtl.nus.edu.sg Language: English - Date: 2011-03-30 04:50:54 Microcontrollers Interrupts Embedded systems Instruction set Emulator ARM architecture Single-board microcontroller Computer Intel Computer architecture Instruction set architectures Central processing unit
673	DECchip[removed]and DECchip[removed]Core Logic Chipsets Data Sheet Order Number: EC–QAEMB–TE Revision/Update Information: Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:54 Instruction set architectures Computer memory Alpha 21064 Computer buses Minicomputers DEC Alpha Conventional PCI CPU cache VAX Computer hardware Computer architecture Computing
674	Product guide HP ProLiant scale-up solutions, powered by AMD Opteron™ Ready for growth with faster, smarter x86 scale-up servers Add to Reading List Source URL: h20195.www2.hp.com Language: English Server hardware ProLiant Instruction set architectures Blade server Advanced Micro Devices HP Integrated Lights-Out Opteron Hewlett-Packard Hyper-V System software Computing Computer architecture
675	Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy Ehsan Totoni, Josep Torrellas, Laxmikant V. Kale Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA E Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-08-13 13:31:19 Computer memory Computer hardware CPU cache Central processing unit Instruction set architectures Cache algorithms Memory hierarchy Blue Gene Xeon Computer architecture Computing Cache
676	Capability Hardware Enhanced RISC Instructions: CHERI Instruction-set architecture Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2015-01-15 09:17:36 MIPS architecture Ring Instruction set Capability-based security 64-bit Hypervisor Kernel Reduced instruction set computing Memory protection Computer architecture Central processing unit Instruction set architectures
677	Prof. Dr.-Ing. Dr. h. c. mult. P. J. Kühn Prof. Dr.-Ing. Dr. h. c. mult. P. J. Kühn International Symposium on Memory Management June 10–11, 2006 Ottawa, Canada Add to Reading List Source URL: www.cs.technion.ac.il Language: English - Date: 2010-02-20 10:44:16 Computing Pointer Garbage collection Classic RISC pipeline Microarchitecture Processor register CPU cache Instruction set Memory barrier Computer hardware Computer architecture Central processing unit
678	Alpha[removed]EV6 Microprocessor Hardware Reference Manual Order Number: DS–0027C–TE This manual is directly derived from the internal[removed]EV6 Specifications, Revision 4.5. You can access this hardware reference manu Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:04:20 Computer engineering DEC Alpha PALcode Alpha 21264 CPU cache Branch predictor Processor register Instruction set Computer architecture Computer hardware Central processing unit
679	AD2100-12-2M-104P-DMA, 12-Bit, 100 MS/sec, PC/104+ Digitizer[removed]Chase Scientific Company - Innovators in Embedded Test & Measurement Add to Reading List Source URL: www.chase2000.com Language: English - Date: 2014-03-20 17:00:23 Microcontrollers Computer buses Computing Instruction set architectures Computer architecture IBM PC compatibles Computer hardware
680	MIPS Code for Tiger COMS W4115 Prof. Stephen A. Edwards Spring 2002 Columbia University Department of Computer Science Add to Reading List Source URL: www.cs.columbia.edu Language: English - Date: 2002-04-07 23:14:04 Instruction set architectures MIPS architecture J Processor register T0 MOV Computer architecture Computing Software engineering

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